Globally Asynchronous Elastic Logic Synthesis

The main aim of this project is to deliver an integrated design methodology for synthesising digital systems with mixed synchronous-asynchronous architectures. The proposed technique combines Globally Asynchronous Locally Synchronous (GALS) design with Elastic Logic principles. Elastic Logic and Asynchronous design are envisioned to share a common timing discipline which should simplify the GALS wrappers and lead to performance gains. Currently, research work is being dedicated to the development of EDA strategies for automating the partitioning of a digital system into GALS blocks. This project is funded by the EPSRC grant EP/I038551/1. Background System-on-Chip (SoC) methodology is being increasingly chosen for complex digital system design owing to its scope for massive integration of functionality on a single chip. However the ease of component reuse in SoCs is plagued by nanoscale design issues such as excessive power consumption, heat dissipation and EMI. Various techniques have been proposed to solve these issues in the traditional synchronous design framework such as clock gating, power gating, dynamic frequency/voltage scaling etc. These solutions cost long designer hours and are implemented by trading o reliability, power or performance owing to the strict timing discipline of the synchronous design ow. Asynchronous design techniques resolve most of the design issues inherently, as they do not rely on a global clock. But they too would not pose an optimal design choice; due to the inability to reuse synchronous IP cores, lack of mature CAD tools, high overhead from communication protocol and high transitioning costs. Globally Asynchronous Locally Synchronous (GALS) systems is considered a better alternative to designing SoCs. GALS system design, quoted as 'best of both worlds', is an approach that can exploit the advantages of asynchronous design and at the same time maximally reuse the products of synchronous design ow. This design technique divides a digital system into locally synchronous islands which communicate asynchronously by handshake mechanism. Due to the presence of multiple clock domains, GALS design provides genuine scope for power savings [1] and energy e ciency compared to its synchronous counterpart by solutions such as idling the clock when data not requested, optimum operating frequency for individual modules, dynamic voltage and frequency scaling etc [2, 3]. The problem with the existing GALS methods is that they are all of an assemble-and-verify paradigm. Lack of CAD tools supporting mixed synchronous-asynchronous design and absence of a GALS design method targeting a process of synthesis with optimisation have made it di cult for GALS to be adapted by industry.